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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC14551B Quad 2-Channel Analog Multiplexer/Demultiplexer The MC14551B is a digitally-controlled analog switch. This device implements a 4PDT solid state switch with low ON impedance and very low OFF Leakage current. Control of analog signals up to the complete supply voltage range can be achieved. * Triple Diode Protection on All Control Inputs * Supply Voltage Range = 3.0 Vdc to 18 Vdc * Analog Voltage Range (VDD - VEE) = 3.0 to 18 V Note: VEE must be VSS * Linearized Transfer Characteristics * Low Noise -- 12 nVCycle, f 1.0 kHz typical * For Low RON, Use The HC4051, HC4052, or HC4053 High-Speed CMOS Devices * Switch Function is Break Before Make L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648 v D SUFFIX SOIC CASE 751B ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS* Symbol VDD Parameter Value Unit V V DC Supply Voltage (Referenced to VEE, VSS VEE) - 0.5 to + 18.0 Vin, Vout Input or Output Voltage (DC or Transient) (Referenced to VSS for Control Input & VEE for Switch I/O) Input Current (DC or Transient), per Control Pin Switch Through Current Power Dissipation, per Package Storage Temperature Lead Temperature (8-Second Soldering) - 0.5 to VDD + 0.5 Iin Isw PD Tstg TL 10 25 500 - 65 to + 150 260 mA mA mW TA = - 55 to 125C for all packages. _C _C * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages - 12 mW/_C From 100_C To 125_C PIN ASSIGNMENT 9 15 1 2 3 6 10 11 12 CONTROL W W0 W1 X0 X1 Y0 Y1 Z0 Z1 X W1 14 4 COMMONS OUT/IN Y Z 5 13 Control 0 1 ON W0 X0 Y0 Z0 W1 X1 Y1 Z1 VDD = Pin 16 VSS = Pin 8 VEE = Pin 7 X0 X1 X Y Y0 VEE VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD W0 W Z Z1 Z0 Y1 CONTROL SWITCHES IN/OUT NOTE: Control Input referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be v VSS. REV 3 1/94 (c)MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995 MC14551B 1 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII ELECTRICAL CHARACTERISTICS - 55_C 25_C 125_C Characteristic Symbol VDD Test Conditions Min Max Min Typ # Max Min Max Unit SUPPLY REQUIREMENTS (Voltages Referenced to VEE) Power Supply Voltage Range Quiescent Current Per Package VDD IDD -- 5.0 10 15 VDD - 3.0 VSS VEE Control Inputs: Vin = VSS or VDD, Switch I/O: VEE VI/O VDD, and Vswitch 500 mV** 3.0 -- -- -- 18 5.0 10 20 3.0 -- -- -- -- 0.005 0.010 0.015 18 5.0 10 20 3.0 -- -- -- 18 150 300 600 V A v v v Total Supply Current (Dynamic Plus Quiescent, Per Package) ID(AV) 5.0 10 15 TA = 25_C only (The channel component, (Vin - Vout)/Ron, is not included.) Typical (0.07 A/kHz) f + IDD (0.20 A/kHz) f + IDD (0.36 A/kHz) f + IDD A CONTROL INPUT (Voltages Referenced to VSS) Low-Level Input Voltage VIL 5.0 10 15 5.0 10 15 15 -- Ron = per spec, Ioff = per spec Ron = per spec, Ioff = per spec Vin = 0 or VDD -- -- -- 3.5 7.0 11 -- -- 1.5 3.0 4.0 -- -- -- 0.1 -- -- -- -- 3.5 7.0 11 -- -- 2.25 4.50 6.75 2.75 5.50 8.25 0.00001 5.0 1.5 3.0 4.0 -- -- -- 0.1 7.5 -- -- -- 3.5 7.0 11 -- -- 1.5 3.0 4.0 -- -- -- 1.0 -- V High-Level Input Voltage VIH V Input Leakage Current Input Capacitance Iin Cin A pF SWITCHES IN/OUT AND COMMONS OUT/IN -- W, X, Y, Z (Voltages Referenced to VEE) Recommended Peak-to- Peak Voltage Into or Out of the Switch Recommended Static or Dynamic Voltage Across the Switch** (Figure 3) Output Offset Voltage ON Resistance VI/O -- Channel On or Off 0 VDD 0 -- VDD 0 VDD Vp-p Vswitch -- Channel On 0 600 0 -- 600 0 300 mV VOO Ron -- 5.0 10 15 5.0 10 15 15 Vin = 0 V, No Load Vswitch 500 mV**, Vin = VIL or VIH (Control), and Vin = 0 to VDD (Switch) v -- -- -- -- 800 400 220 70 50 45 100 -- -- -- -- -- -- -- -- 10 250 120 80 25 10 10 0.05 -- 1050 500 280 70 50 45 100 -- -- -- -- -- -- -- -- -- 1200 520 300 135 95 65 1000 V ON Resistance Between Any Two Channels in the Same Package Off-Channel Leakage Current (Figure 8) Ron -- -- -- Vin = VIL or VIH (Control) Channel to Channel or Any One Channel Switch Off -- Ioff nA Capacitance, Switch I/O Capacitance, Common O/I Capacitance, Feedthrough (Channel Off) CI/O CO/I CI/O -- -- -- -- -- -- -- -- -- -- -- -- -- -- 10 17 0.15 0.47 -- -- -- -- -- -- -- -- -- -- -- -- pF pF pF Pins Not Adjacent Pins Adjacent -- -- #Data labeled "Typ" is not to be used for design purposes, but is intended as an indication of the IC's potential performance. ** For voltage drops across the switch (Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the ** current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum ** Ratings are exceeded. (See first page of this data sheet.) MC14551B 2 MOTOROLA CMOS LOGIC DATA IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII ELECTRICAL CHARACTERISTICS (CL = 50 pF, TA = 25_C, VEE Characteristic v VSS) Symbol VDD - VEE Vdc Min Typ # Max Unit ns Propagation Delay Times Switch Input to Switch Output (RL = 10 k) tPLH, tPHL = (0.17 ns/pF) CL + 26.5 ns tPLH, tPHL = (0.08 ns/pF) CL + 11 ns tPLH, tPHL = (0.06 ns/pF) CL + 9.0 ns Control Input to Output (RL = 10 k) VEE = VSS (Figure 4) tPLH, tPHL 5.0 10 15 tPLH, tPHL 5.0 10 15 -- BW 10 10 -- -- -- -- -- -- -- -- 35 15 12 350 140 100 0.07 17 90 40 30 ns 875 350 250 -- -- % MHz Second Harmonic Distortion RL = 10 k, f = 1 kHz, Vin = 5 Vp-p Bandwidth (Figure 5) RL = 1 k, Vin = 1/2 (VDD - VEE) p-p, 20 Log (Vout / Vin) = - 3 dB, CL = 50 pF Off Channel Feedthrough Attenuation, Figure 5 RL = 1 k, Vin = 1/2 (VDD - VEE) p-p, fin = 55 MHz Channel Separation (Figure 6) RL = 1 k, Vin = 1/2 (VDD - VEE) p-p, fin = 3 MHz Crosstalk, Control Input to Common O/I, Figure 7 R1 = 1 k, RL = 10 k, Control tr = tf = 20 ns -- 10 -- - 50 -- dB -- 10 -- - 50 -- dB -- 10 -- 75 -- mV #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD for control inputs and VEE (Vin or Vout) VDD for Switch I/O. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS, VEE, or VDD). Unused outputs must be left open. MOTOROLA CMOS LOGIC DATA MC14551B 3 VDD IN/OUT VDD VDD OUT/IN VEE VDD LEVEL CONVERTED CONTROL IN/OUT CONTROL VEE OUT/IN Figure 1. Switch Circuit Schematic 16 VDD CONTROL 9 LEVEL CONVERTER CONTROL 8 W0 15 VSS 7 VEE 14 W W1 1 X0 2 4X X1 3 Y0 6 Y1 10 Z0 11 13 Z Z1 12 5Y Figure 2. MC14551B Functional Diagram MC14551B 4 MOTOROLA CMOS LOGIC DATA TEST CIRCUITS ON SWITCH CONTROL SECTION OF IC LOAD V SOURCE VDD VEE VEE VDD RL CL PULSE GENERATOR CONTROL Vout Figure 3. V Across Switch Figure 4. Propagation Delay Times, Control to Output Control input used to turn ON or OFF the switch under test. RL ON CONTROL RL Vout CL = 50 pF CONTROL OFF RL Vin VDD - VEE 2 VDD - VEE 2 Vin Vout CL = 50 pF Figure 5. Bandwidth and Off-Channel Feedthrough Attenuation Figure 6. Channel Separation (Adjacent Channels Used for Setup) OFF CHANNEL UNDER TEST VDD CONTROL SECTION OF IC VEE OTHER CHANNEL(S) VEE VDD VEE VDD CONTROL RL R1 Vout CL = 50 pF Figure 7. Crosstalk, Control Input to Common O/I Figure 8. Off Channel Leakage MOTOROLA CMOS LOGIC DATA MC14551B 5 VDD KEITHLEY 160 DIGITAL MULTIMETER 10 k VDD VEE = VSS 1 k RANGE X/Y PLOTTER Figure 9. Channel Resistance (RON) Test Circuit TYPICAL RESISTANCE CHARACTERISTICS 350 RON, "ON" RESISTANCE (OHMS) RON, "ON" RESISTANCE (OHMS) 300 250 200 150 100 50 0 - 10 - 8.0 - 6.0 - 4.0 - 2.0 0 2.0 4.0 6.0 TA = 125C 25C - 55C 350 300 250 200 150 100 50 0 - 10 - 8.0 - 6.0 - 4.0 - 2.0 0 2.0 4.0 6.0 8.0 10 TA = 125C 25C - 55C 8.0 10 Vin, INPUT VOLTAGE (VOLTS) Vin, INPUT VOLTAGE (VOLTS) Figure 10. VDD @ 7.5 V, VEE @ - 7.5 V Figure 11. VDD @ 5.0 V, VEE @ - 5.0 V 700 RON, "ON" RESISTANCE (OHMS) RON, "ON" RESISTANCE (OHMS) 600 500 400 300 200 100 0 - 10 - 8.0 - 6.0 - 4.0 - 2.0 0 2.0 TA = 125C 25C - 55C 4.0 6.0 8.0 10 350 300 250 200 150 5.0 V 100 50 0 - 10 - 8.0 - 6.0 - 4.0 - 2.0 0 2.0 4.0 6.0 8.0 10 7.5 V TA = 25C VDD = 2.5 V Vin, INPUT VOLTAGE (VOLTS) Vin, INPUT VOLTAGE (VOLTS) Figure 12. VDD @ 2.5 V, VEE @ - 2.5 V Figure 13. Comparison at 25_C, VDD @ - VEE MC14551B 6 MOTOROLA CMOS LOGIC DATA APPLICATIONS INFORMATION Figure A illustrates use of the on-chip level converter detailed in Figure 2. The 0-to-5 volt Digital Control signal is used to directly control a 9 Vp-p analog signal. The digital control logic levels are determined by VDD and V SS. The V DD voltage is the logic high voltage; the V SS voltage is logic low. For the example, V DD = + 5 V = logic high at the control inputs; VSS = GND = 0 V = logic low. The maximum analog signal level is determined by V DD and V EE. The V DD voltage determines the maximum recommended peak above V SS. The V EE voltage determines the maximum swing below V SS. For the example, V DD - V SS = 5 volt maximum swing above V SS; VSS - VEE = 5 volt maximum swing below VSS. The example shows a 4.5 volt signal which allows a 1/2 volt margin at each peak. If voltage +5 V transients above V DD and/or below V EE are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure B. These diodes should be small signal types able to absorb the maximum anticipated current surges during clipping. The absolute maximum potential difference between V DD and V EE is 18.0 volts. Most parameters are specified up to 15 volts which is the recommended maximum difference between V DD and V EE. Balanced supplies are not required. However, V SS must be greater than or equal to V EE . For example, V DD = + 10 volts, V SS = + 5 volts, and V EE = - 3 volts is acceptable. See the table below. -5 V VDD VSS +5 V 9 Vp-p ANALOG SIGNAL SWITCH I/O VEE + 4.5 V COMMON O/I MC14551B 9 Vp-p ANALOG SIGNAL GND EXTERNAL CMOS DIGITAL CIRCUITRY 0-TO-5 V DIGITAL CONTROL SIGNAL CONTROL - 4.5 V Figure A. Application Example VDD VDD Dx SWITCH I/O Dx COMMON O/I Dx Dx VEE VEE MOTOROLA CMOS LOGIC DATA IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII Figure B. External Schottky or Germanium Clipping Diodes POSSIBLE SUPPLY CONNECTIONS VDD In Volts +8 +5 +5 +5 VSS In Volts 0 0 0 0 VEE In Volts -8 Control Inputs Logic High/Logic Low In Volts + 8/0 + 5/0 + 5/0 + 5/0 Maximum Analog Signal Range In Volts + 8 to - 8 = 16 Vp-p - 12 0 + 5 to - 12 = 17 Vp-p + 5 to 0 = 5 Vp-p -5 -5 + 5 to - 5 = 10 Vp-p + 10 + 10/ + 5 + 10 to - 5 = 15 Vp-p MC14551B 7 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V -A- 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 -B- 1 8 C L -T- SEATING PLANE N E F D G 16 PL K M J 16 PL 0.25 (0.010) M M TB S 0.25 (0.010) TA S P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R -A- 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 B 1 8 F S C L -T- H G D 16 PL SEATING PLANE K J TA M M 0.25 (0.010) M MC14551B 8 MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J -A- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 9 -B- 1 8 P 8 PL 0.25 (0.010) M B S G F K C -T- SEATING PLANE R X 45 _ M D 16 PL M J 0.25 (0.010) TB S A S DIM A B C D F G J K M P R Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MOTOROLA CMOS LOGIC DATA *MC14551B/D* MC14551B MC14551B/D 9 |
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